INTERNATIONAL BURCH UNIVERSITY
Graduate Study - Faculty of Engineering and Natural Sciences
3+2 Electrical and Electronic Engineering
2015-2016

SYLLABUS
Code Name Level Year Semester
EEE 549 Systems on Chip Graduate 1 Fall
Status Number of ECTS Credits Class Hours Per Week Total Hours Per Semester Language
Area Elective 6 3 149 English

Instructor Assistant Coordinator
Harun Šiljak, Assist. Prof. Dr. Harun Šiljak Harun Šiljak, Assist. Prof. Dr.
[email protected] [email protected] no email

This lab-oriented course will focus on the design of large-scale system-on-a-chip (SOC) solutions within field-programmable gate arrays (FPGAs). Modern FPGA densities and commercially available cores enable a single developer to design highly complex systems within a single FPGA. This class will provide the student with the ability to design and debug these inherently complex systems.

COURSE OBJECTIVE
Course serves as both a reminder of students' previous experience with hardware description and as an introduction to systems on chip design. As such, it enables the student to independently design a system on chip with reasonable demands after finishing the course.

COURSE CONTENT
Week
Topic
  1. Introduction to Logic Circuits
  2. Number Representation and Arithmetic Circuits
  3. Flip-flops, Registers
  4. Counters
  5. FSM
  6. FSM
  7. Digital System Design
  8. Presentation 1
  9. Lab preparation
  10. Lab preparation
  11. Lab preparation
  12. Lab preparation
  13. Lab preparation
  14. Concluding remarks
  15. Presentation 2

LABORATORY/PRACTICE PLAN
Week
Topic
  1. Introduction to Quartus and ModelSim
  2. Switches, Lights, and Multiplexers
  3. Numbers and Displays
  4. Latches, Flip-flops, and Registers
  5. Counters
  6. Timers and Real-Time Clock
  7. Adders, Subtractors, and Multipliers
  8. Finite State Machines
  9. Memory Blocks
  10. A Simple Processor

  1. An Enhanced Processor
  2. Implementing Algorithms in Hardware
  3. Basic Digital Signal Processing

TEACHING/ASSESSMENT
Description
  • Practical Sessions
  • Excersises
  • Presentation
  • Problem solving
Description (%)
Method Quantity Percentage (%)
Presentation125
Laboratory1225
Term Paper125
Final Exam125
Total: 100
Learning outcomes
    TEXTBOOK(S)
    • Brown, Stephen D., and Zvonko G. Vranesic. \\\\\\\"Fundamentals of Digital Logic with Verilog Design.\\\\\\\"

    ECTS (Allocated based on student) WORKLOAD
    Activities Quantity Duration (Hour) Total Work Load
    Lecture (14 weeks x Lecture hours per week)14114
    Laboratory / Practice (14 weeks x Laboratory/Practice hours per week)14228
    Midterm Examination (1 week) 0
    Final Examination(1 week)122
    Preparation for Midterm Examination 0
    Preparation for Final Examination13535
    Assignment / Homework/ Project13535
    Seminar / Presentation13535
    Total Workload: 149
    ECTS Credit (Total workload/25): 6